# Bias and small-signal equations for the” Electronics Help

emitter-stabilized CE amplifier Rill = (,B + l)RE,BR£ (~) VB  Rt + Merrill Vc (Rt ~2 R 2 ) Vcc (Rill » R2) V =< VB – 0.7 (Si) I R£ ( ; (Rt ~2 R) Vcc – VBE) Ic = {J Rd l R2 + ({J + l)RE Vc = Vcc – IeRc – feRE – (Re + RE) A =R-c- Rc v Rt: + r, Rt: Rc =(R » r.. R bypassed)  (R£ bypassed) fill = (13 + l)(R + f,) :=f3R (R » r.. R bypassed) f3f, (RE bypassed) fj,,{stage) = R8 II fjn where R/J = R\ II R2 UL = A [ fj,,(stage) ]( RI. ) Us v r, + fj,,(stage) Rc + R -( ‘I. )[ r”,(stage)] (Rf,’bypassed) Rf: + r, rs +(stage) = ( ) [(stage)] (RE bypassed)  Solution. Since the dc circuits are identical, we calculate the emitter current for each of Figure 6-8(a) and (b) as follows: s;» ( : = 100(680 a) = 68 kO Rin II R2 = (68 kO) ” (4.7 kO) = 4.39 kO VH = ( R;,,” R2 ) 10V = ( 4.;9 X 103 1)·10 V = 1.39V RI + Rill” R2 27 X 10 + 4.39 x 10· Vf. = VH – 0.7 = (1.39 – 0.7)V = 0.69 V h= Vf: = 0.69 V “‘”1 mA
. RE 6800 Therefore, r, “‘”0.026/(1 mA) = 2J O. For Figure 6-8(a), we have ‘ill(stage) = R,” R!” (3(RJ:”+ r) = (27 x 10-‘)” (4.7 X 103)” 100(680 + 26) = 3.79 kn The overall voltage gain is VI__ ( Rc;)[ rin(stage) ]( Rl. ) Vs – – R£ + r< rs + rlll(stage) Rc + RL ( 3.3 X 1Ql)( 3.79 X lQl)( 15 X 103 ) = – 706 600 + 3.79 X lQl 3.3 X lQl + 15 X 10-‘
== -(4.67)(0.862)(0.82) = -3.3 For Figure 6-8(b) and r”,(stage) = R, ” R2 ” {3r,. = (27 X 10′)” (4.7 X 10’) 112600~ 158 kV VI. _ ( 3.3 X 103
Vs – – 26 600 + 1.58 X lO~ 3.3 X 103 + 15 X lQl = -(126.9)(0.72)(0.82) = -74.9 Note that the voltage gains in both cases are considerably lower than those of previous examples. However, both circuits are well stabilized: RB/ R£ ..,. 5.9. Note also that bypassing Rf. with the capacitor in Figure 6-8(b) did not restore all the voltage gain that the transistor itself is capable of producing [(3.3 )/(26 a) = 126.9]. Bypassing R£ reduced (stage) from 3.79 kO to 1.58 \cO, which, as the Computations show, caused the voltage division at the input to change from 0.862 to 0.72. The relatively large value of rs (600 n ) is responsible for a greater loss  when ,.,,(stage) is reduced.Vs that can be used to drive the amplifier in Figure 618(b) without creating serious visible distortion in the load voltage, VL. Assume that the coupling capacitors are each 10 /LF, the emitter bypass capacitor is 100 /LF, and the signal frequency is 10 kHz. (These values ensure that the capacities resistances are negligible and bave no effect on amplifier gain.)Solution. Figure 6-9(a) shows the circuit redrawn f01 analysis by SPICE and the
input data file. Since we must observe the output waveform to detect distortion, it is necessary to perform a .TRAN analysis and specify a SIN source rather than an .AC analysis with a source designated AC. Figure 6-9(b) shows the results of a program run when the peak value of the SIN source j 0.1 V. It is clear that the
load voltage is severely distorted due to clipping. Repeating trial-and-error runs  using progressively smaller amplitudes for Us leads to the results shown in Figure 6-9ic). A peak value of about 0.01 V for Us is found to be the largest that can be used without creating visible distortion in VL. Note that the magnitude of the voltage gain in that case is IVI., = 0.6620 – (-0.8252) V p-p = 74.36 V.I 0.02 V which is in excellent agreement with the result calculated in Example 6.

Posted on November 18, 2015 in Bias Design in Discrete and Integrated Circuits