The output of a switching circuit, such as a MOSFET inverter, always has a certain amount of capacitance in parallel with it. This capacitance may be inherent in the input of the device that serves as the load for the switching circuit, and it may be stray capacitance associated with conducting paths and terminal connections on the output side of the circuit. Capacitance in parallel with the output is called capacitive loading and is responsible for slowing the speed at which the circuit can switch from high to low and/or from low to high. This fact is illustrated in Figure 8-42. To minimize the detrimental effects of capacitive loading, the output resistance of the switching circuit should be as small as possible. As can be seen in Figure 8-42, the time required for the output of the switching circuit to change from low to high depends on the time constant R”C/. that governs the charging of capacitance CI. through resistance Ro. Recall that approximately 5 time constants must elapse for the capacitor to be essentially fully charged. Therefore, the smaller the value of Ro, the smaller the time constant, and the more quickly the output voltage can reach its high output level. Similarly, when the output goes low, the capacitance must discharge through R; and the time required for the output to reach its low level again depends on the time constant RoC

Capacitive Loading of the MOSFET Inverter

In many switching circuits, the output resistance when the output is changing from low to high is different from the output resistance when the output is changing from high to low. Thus, the device may be able to turn ON faster than it can turn OFF, or vice versa. This is the case in the MOSFET inverter, as illustrated in Figure 8-43, because the resistance of Q2 is usually much greater than that of QI’ When QI is switched OFF by a low input, the output of the inverter rises as the load capacitance is charged through the large resistance of Q2. On the other hand, when QI is switched ON by a high input, the load capacitance discharges rapidly through the small ON resistance of QI’ In characterizing the time required for a waveform to change from low to high and from high to low, it is common practice to specify its rise time, t., and fall time, If. As illustrated in Figure 8-44, t, is the total time required for the waveform to rise from 10% of its final (high) value to 90% of its final value, and If is the total time to fall from 90% of its high value to 10% of its high value. It can be shown that the following expressions are good approximations for These equations show that I, and If are directly proportional to CI. and. inversely proportional to {3.The dependency on {3follows from the fact that channel resistance
is inversely related to {3. Since {31 is typically 10 times greater than {32, the channel resistance of 01 is about 10 that of 02. The next example illustrates the disparity between the rise and fall times of an NMOS inverter.The NMOS inverter in Example 8-10 has-a 10-pF capacitive load and is driven by a rectangular waveform that alternates between 0 V and +8 V with a frequency of 400 kHz. The pulsewidth is 0.5 }J.S. Obtain a plot of the output over one full cycle of input Thus, the .TRAN statement produces one full cycle of output at O.l-/-ts intervals, The PULSE specification for VI shows that the rise and fall times of theinput pulse are each set to 1 ps, which is very small compared 10 the pulse width. These specifications make the input pulse very nearly ide a !. If the rise and fall limes of the input were set to 0 or allowed to default, SPICE would set them equal to the much longer time TSTEP = D.t J.tS. Note that two .MODEL statements are required in the data file, since the MOSFETs have different values of (J. The plot of the output is shown in Figure 8-45(b). Note that the rise time of the output is much longer than the fall time. Also note that the low output level is VON = D.49 V, in agreement with the calculations in Example 8-10.

Posted on November 19, 2015 in FET CIRCUITS AND APPLICATIONS

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