Recall that complementary MOS (CMOS) integrated circuits contain both NMOS and PMOS devices embedded in the same chip (see Figure 7-47). The CMOS design is now widely used in general-purpose digital circuits because it provides faster switching times than either PMOS or NMOS devices alone. It is also used in special-purpose MSI and LSI circuits. Figure 8-46 shows a CMOS inverter, the fundamental building block of the CMOS logic family. Notice that there is but a single, positive supply voltage, VOD, and that the source of the PMOS transistor is connected to V/J/J. This connection is necessary for the proper operation of a PMOS device, whose drain must be negative with respect IV its source. (In Chapter 7 we showed the isolated PMOS transistor with a negative supply voltage connected to its drain; the same bias is achieved by making the source positive with respect to the drain.) Notice in Figure g-46 that the substrate terminal of 02 is shown connected to + Vnn. This P-channel device has an N-type substrate. which must be connected to the most positive voltage in the circuit to ensure that the junction between the substrate and the induced P channel is reverse biased. The “substrate” of the Nchannel device (01) is actually the P-type tub in which the device is embedded, as shown in Figure 7-44. Therefore, the substrate terminal of 01 is shown connected to the most negative voltage (ground) to ensure reverse bins. As an aid in understanding the operation of a CMOS inverter, let us review and summarize the gate-to-source conditions that cause enhancement NMOS and PMOS transistors to either conduct (turn ON) or turn OFF. These conditions are given in the following table:grounded. such as 0, ill Figure 8-46. Then () Y applied to its ga e will turn it OFF because ViiS = ()< VI’ When + 10 Y is applied to its gate, it will turn ON (conduct) because \ ‘cs = + 10 > Vr. Consider now a PMOS transistor that has Vr =: -2 Y and that has +JO V connected to its source. such as Q: in Figure 8-46. Then 0 y applied to its gate will turn it ON. because VGS = -10 Y, which is more negative than -2 Y. When + 10 V is applied to its gate. the result is ViiS = 0 Y, and it is turned OFF because () V is more positive than -2 Y. Notice in Figure H-46 that the gates of Q, and O2 are connected together at the input to the inverter. Therefore, when ViII is high (say, + 10 V), Q, is ON and 02 is OFF. On the other hand, when ViII is low (0 V), 0, is OFF and Q2 is ON. To see how these facts rclate to inverter operation, think of each device as a switch
that is closed when it is ON and open when it is OFF. See Figure 8-47. As shown in the figure, a low input closes 02 and opens Q” so the output is connected through 02 to + VOl)’ A high input doses QI and opens Q2, so the output is connected through 0, to ground (0 V). Thus, one device is always ON, and the output Ievel is always the opposite of the input level. The input and output levels of CMOS inverters alternate between a I w near o Y and a high near +VIl/J. One advantage of CMOS circuitry is that the high leve can be anywhere from about 3 Y to about 18 Y, a very wide range in coup.orison to other’ digital logic families. The higher the level of VIII)’ the faster the switching lime and the more immune the circuit is to electrical noise (random fluctuations in signal levels), but the greater the power dissipation. In genera, CMOS circuitry is considered to have very low power dissipation. The reason that CMOS circuits have faster switching times than their NMOS and PMOS counterparts is that the output resistance is small both when the output is changing from low to high and when it is changing from high to low. When the output is changing from low to high, the load capacitance is charged through the small ON resistance of Q2 (Figure 8-47 When the output is changing from high to low, the load capacitance discharges through the small ON resistance of Q
(Figure 8-47(c)). Thus, the time constant is small in both cases, and the rise and fall times are about equal.