In the third and final way to arrange the biasing of a transistor, the collector is made the common point. The result is called the common-collector (CC) configuration and is illustrated in Figure 4-23. It is apparent in Figure 4-23(a) that

Therefore, in order to keep the collector-base junction reverse biased (VeB > 0), it is necessary that VBB be larger than Vcc – 0.7. Figure 4-24 shows inat the base-collector voltage is the input voltage and the base current is the input current. The emitter-coIlector voltage is the.output voltage and the emitter current is the output current.

Figure 4-25 shows a typical set of input characteristics for an NPN transistor
in the CC configuration. It is clear that these are not the characteristics of a forwardbiased diode, as they were in the CB and CE configurations. We can see that each curve is drawn for a different fixed value of VCE and that each shows the base current going to 0 very quickly as VeB increases slightly. This behavior can be explained by remembering that VnE must remain in the neighborhood of 0.5 V to 0.7 V in order for any appreciable base current to flow. But, from equation 4-13,

Therefore if the value of Ve/J is allowed to increase to a point where it is near the value of Va” the value of VII”: approaches 0, and no base current will flow. In Figure 4-25 refer to the curve that corresponds to VII:’ = .5 V. When VIII = 4.3 V, we have, from equation 4-15. ViII, = 5 – 4.3 = 0.7 V. and we therefore expect a substantial base current. In the figure. we see that the point VCII = 4.3 V and VCt’ = 5 V yields a base current of 80 /LA. If VCIJ is now allowed to increase to 5 V, then VilE = 5 – 5 = 0 V, and the base-emitter junction is no longer forward biased. NOIe in the figure that 1/1 = 0 when VC/: = VCII = 5 V.

Figure 4-26 shows a typical set of CC output characteristics for an NPN transistor. These show emitter current, l «, versus collector-to-emitter voltage. Vct’, for different fixed values of 10• Note that these curves closely resemble the CE output characteristics shown in Figure 4-19. This resemblance is expected, since the only distinction is, that :,: in Figure 4-26 is along the vertical axis instead of lc, and


In our discussion of BJT theory up to this point, we have been using the word bias simply to specify the polarity of the voltage applied across each of the PN junctions in a transistor. In that context, we have emphasized that the base-emitter junction must be forward biased and the collector-base junction must be reverse biased, to achieve normal transistor action. We wish now to adopt a more restrictive interpretation of “bias.” Henceforth we will be concerned with adjusting the value of the bias, as needed, to obtain specific values of input 3Hd output currents and voltages. In other words, we accept the fact that both junctions must be biased in the proper .direction and concentrate on a practical means for changing the degree of bias, so that the output voltage, for example, is exactly the value we want i! to be. When we have achieved a specific output voltage and output current, we say that we have set the bias point to those values .

Common-Base Bias Circuit

In practical circuits we control the bias by connecting external resistors in series with the external voltage sources Vcc, Vee, etc. We can then change resistor values instead of voltage source values to control the de input and output voltages and currents. The circuit used to set the bias point this way is called a bias circu,t. Figure 4-27 shows common-base bias circuits in which a resistor RE is connectedin series with the emitter and a resistor Rc is in series with the collector. Notice that we still regard ernnter current as input current and base-emitter voltage as input voltage as in past discussions of the CB configuration. See Figure 4-9. Likewise, collector current and collector-base voltage are still outputs. The only difference is that the input voltage is no longer the same as VEE, because there is a voltage drop across RF• and the output voltage is no longer the same as Vcc, due to the drop across Re. The external voltage sources Vlili and Vce are called supply voltages. Of course, the characteristic curves are still perfectly valid for relationships between input and out\?ut voltages.and currents.

When we regard Ie and VeB as variables, and Vee and Rc as constants, we see that. equation 4-18 is the equation of a straight line. When plotted on a set of Ie- VeB axes, the line has slope -liRe, and it intercepts the Ie-axis at VeclRe. Equation 4-18 is the equation for the (NPN) CB load line. This load line has exactly the same interpretation as the diode load lint: we studied in Chapter 3: It is the line through all possible combinations of voltage (VeB) and current (Ie).The actual bias point must be a point lying somewhere on the line. The precise location of the point is determined by the inputs VBE and h. We can find the point where the load line intercepts the VeB-axisby setting Ie = 0 in equation 4-18 and solving for VCR. Do this as an exercise, and verify that th~ Ven-intercept is Ven = .Vee. Thus. the load line can be drawn simply by drawing a line through the two points VeB =. D, Ie = VcelRe and lc = 0, VeB = Vee

We can determine the bias point by plotting the load line on the output characteristics of the transistor used in the circuit. To illustrate, the load line determined in Example 4-8 is shown drawn on a set of CB output charactenstics in Figure 4-30.

To locate the bias point on the load line shown in Figure 4-30, we must determine the emitter current hin the circuit of Figure 4-28. One way to find l e would be to draw an input load line on an input characteristic and determine the value of hwhere the line intersects the characteristic. This is the same technique used in Chapter 3 to find the de current and voltage across a forward-biased diode in series with a resistor, which is precisely what the ; put side of the transistor circuit is. However, this approach is not practical for several reasons, not the least of which is the fact that input characteristics are seldom available

The most practical way tv determine le is to regard the base-emitter junction as a forward-biased diode having a fixed drop of 0.7 V ( ilicor) and solve for the diode  we did in Chapter 3. Refer to Figure 4-31. In Figure 4-31. it is evident that

Note that we are neglecting the “feedback” effect of VCH on the emitter current. Also note that the positive side of Vn, is connected to the circuit common, or ground, so it would normally be referred to as a negative voltage. However. in our equations. we treat VEl: a!’ the absolute value of that voltage. Returning to our example circuit of Figure 4-28. we a ply equation 4-19 to find

In Figure 4-30, the bias point, labeled Q, is seen to be the intersection of the load line with the curve l e = 2 mA. At that point, Ie “‘” 2 mA and Vell = 12’ V.

The bias point is often called the quiescent point, Q-point, or operating point. It specifies the de output voltage and current when no uc voltage is superimposed on the input. As we shall discover in Chapter 5, the circuit is used as an ac amplifier by connecting an ac voltage source in series with the emitter As the ac voltage alternately increases and decreases, the emitter current does the same. As a result, the output voltage and current change along the load line over a range determined by the change in /r; values.

Equations 4-21 can be used for PNP transistors (Figure 4-27(b» by substituting VU1 for Vllf: and VIIC for VCII’ Substitute the absolute value of Vee in the equation. For example, if we have Ie = I mA, Rc = 1 kil, and Vee = -15 V in the PNP circuit of Figure 4-27(b), then VIIC = 15 – (I mA)(l kil) = +5 V. Since l~ base terminal is common in this circuit, the output voltage is often expressed with the base as reference, i.e., as Vcn. Of course, Ven = – Vuc, so Veu = -5 V in this

Common-Emitter Bias Circuit

Figure 4-32 shows practical bias dIed:” ~ •.NPl” and P P tr~~!;s ors in the ‘0 ~1- men-emitter configuration. Notice that these bias circuits use only a single supply voltage (Vce), which is a distinct practical advantage. The values of Rs and Rc rnu t be chosen so that the voltage drop across Ru is greater than the voltage drop across Rc, in order to keep the collector-base junction reverse biased. The selection of values for RII and Rr: is part of the procedure used to design a CE bias circuit. which we will cover in Chapter

As discussed in Chapter 3,’it is important to be able 1O ‘Visialize the operation of elect«. ,j circuit when their diagrams are drewn without the ground paths shown, since that is the usual practice. The schematic diagrams in Figure 4-32 arc useful for identifying closed loops, around which Kirchhoffs voltage la v can be written, but the diagrams are rarely drawn as shown. Figure 4-33 shows the conventional way for drawing schematic diagrams of the CE bias circuits. As we have done in Figure 4-33, we will hereafter omit the ground paths in transistor schematics

Example 4-10

The silicon transistor in the CE bias circuit shown in Figure 4-36 has a f3 of 100.

1. Assuming that the transistor has the output characteristics shown in Figure 4-37,
determine the bias point graphically. ‘
2. Find the bias point algebraically.
3. Repeat (I) and (2) when R/I is changed to 161.43 kH.


1. The equation of the load line is

The load line intersects the Ie-axis at 6 mA and the V(,/:-axis at 12 V. It is shown plotted on the output characteristics in Figure 4-37. To locate the bias point. we find ‘1/:

At the intersection of the 1/1 = 30 /LA curve- with the load line, labeled QI in Figure 4-37, we see that the bias point ‘is 1(, “‘” 2.95 rnA and Vcr:, = 6 V.

2. From equations 4-24, we find

These results are in good agreement with the bias values found graphical’y

3. Changing R8 to 161.43 kfl has no effect on the load line. Note that the I .!J l , equation (4-22) does not involve RI/. However, the value of 1/1 is changed io

These arc clearly erroneous results, since the maximum value that Ie can have is 6 mA, and thc minimum value that VC/:’ can have is 0 V. The reason equations 4-24 are not valid in this case is that the bias point is not in the active region. Remember that {3decreases in the saturation region, and, in this example, can no longer be assumed to equal lfk). (As an exercise, use Figure 4-37 to calculate
the value’ of (3 at Q2′)

Example 4-11

Use SPI CE to lind the bias point of the CE circuit in Figure 4-36.


The circuit is redrawn for analysis by SPICE as shown in Figure 4-3X(a). A .DC analysis is performed and the values of V(2), which is Vo;, and I(VDUM),

which is lc, are printed. The results shown in Figure 4-3X(b) reveal that Yd. = 6.06 V and lc = 2.97 mA, in close agreement with the values calculated in Example 4-10.

Posted on November 18, 2015 in BIPOLAR JUNCTION TRANSISTORS

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