# cycle Electronics Help

plotted in 26 points over one full cycle (l/1Q4Hz == 0.1 ms). The plot, appearing in Figure 8-14(a), shows that the peak-to-peak output is 0.5972 V – (-0.5965 V) = 1.1937 V. Thus, the voltage gain is -(1.193 V p-p)/(O.2 V p-p) = -5.97, where the minus sign reflects the phase inversion evident in the plot. Figure 8-14{b) shows the plot that results when the peak value of the input is changed to 3 V. Clearly, the amplifier is overdrive by that input, and se plotted in 26 points over one full cycle (l/1Q4Hz == 0.1 ms). The plot, appearing
in Figure 8-14(a), shows that the peak-to-peak output is 0.5972 V – (-0.5965 V) = 1.1937 V. Thus, the voltage gain is -(1.193 V p-p)/(O.2 V p-p) = -5.97, where the minus sign reflects the phase inversion evident in the plot. Figure 8-14{b) shows the plot that results when the peak value of the input is changed to 3 V. Clearly, the amplifier is overdrive by that input, and clipping at approximately -4.8 V and +7.2 V is apparent 10 the output. Of course, the voltage gain is unchanged, but the clipped waveform is not useful for determining its value. The waveform does reveal that the maximum permissible peak-to-peak output is approximately 9.6 V (twice the value of the smallest clipping level). 2. Figure 8-15(a) shows the circuit and input data file used to determine r;n(stage). Note that we have replaced the SIN generator and its internal resistance of   1 k!l by an ac current source, Is, whose value is allowed to default to 1 A. Since the input resistance is numerically equal lo U,. at node 2. Note this important point: The current source must have a resistance in parallel with it because SPICE open-circuits all ru rrent sources when it computes the • Miriam! transient solution,” and there must he 11 path to ground from every node. In this example, we connect the very large resistance (. = 1000 M!l in parallel with the source to provide that path. Hoff i~so much larger than rj,,(stage) that its presence has negligible effect on the con’ {litigation. The results of the ac analysis in Figure 8-15(b) show that V(2) = Viii = r,.(stage) = 3.76 X 104 0, which equals the parallel combination of RI and R2• As discussed in Example A-3 of Appendix A (note 5), practical voltage limitations and distortion are not factors in an .AC analysis performed by SPICE, so the unrealistically large input voltage does not affect the validity of the result

Unbypassed Source Resistor

Figure 8-16 shows a common-source amplifier with an bypassed source resistor and the small-signal equivalent circuit f the amplifier. For the moment, we do not consider the effects of signal-source resistance and load resistance. Assuming Since the voltage gain of the amplifier with bypassed source resistor is -~ . we see that the effect of omitting the bypass capacitor is to reduce gain by the factor 1/(1 + g”,Rs). Using the typical values gm = 4000 ,. = 3 , and R~ ‘”‘ 500 11, the gain with Rs bypassed is -glorify = -(4000 )(3 ) = -12. This value i reduced in the bypassed case by the factor 1 + = 1 + (4000 ,S)(51111 !h -e 3 to the value -l( = -4. When signal-source resistance rs and load resistance are considered, l!~” usual voltage division takes place at input and output, and we have

Posted on November 18, 2015 in FET CIRCUITS AND APPLICATIONS