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is attached to a line that is separated from the rest of the symbol, to emphasize that the gate is insulated from the channel. The square-law equation for the transfer characteristic of a depletion-type Samoset is identical \0 that for a Forget: This equation correctly predicts Iv when the depletion-type SAMOSET is operated in. the enhancement mode, Note, for example, that when Vc;s is positive in an device, (I – ) > I (since , is negative), and therefore If) is greater /m,~. Figure 7-32 shows transfer characteristics for N- and P-channel devices. Note in each case that I()exceeds loss in the enhancement mode The bias techniques we have already discussed for junction FETs are wholly applicable to depletion-type Marmosets, since the characteristics of the two devices are so similar. We will not repeat our discussion of those techniques.Enhancement-Type Recall that the channel of an N-channel depletion SAMOSET is the region of N material between the drain and the source (see Figure 7-27). In the enhancement , there is no N-type material between the drain and the source; instead, the P-type substrate extends all the way to the layer adjacent to the gate. This structure is shown in Figure 7-33. Apart from the absence of the N-type channel, the construction is the same as that of the depletion Figure 7-34 shows the normal electrical connections between drain, gate, and source. As in the depletion , the substrate is usually connected to the source. Notice that VGS is connected so that the gate is positive with respect to the source. The positive gate voltage attracts electrons from the substrate to the region along the insulating layer opposite the gate. If the gate is made sufficiently positive, enough electrons will be drawn into that region to convert it to N-type material. Thus, an N. ‘H~ channel will be formed between drain and source. The P material IS said to have been inverted to form an -type channel. If the gate is made still more positive more electrons will be drawn into the region and the channel will widen, making it more conductive. In other words, making VGS more positive enhances the conductivity of the channel and increases the flow of current from dram to source. Since electrons are induced into the channel to convert it to N-type material, the SAMOSET shown in Figures 7-33 and 7-34 is often called an induced Channel enhancement-type SAMOSET. When this device is referred to simply as an N-channel enhancement MOSFET, it is understood that the N channel exists only when it is induced from the P substrate by a positive Vas. The induced N channel in Figure 7-34 does not become sufficiently conducive to allow drain current to flow until Vas reaches a certain threshold voltage, VI” In modern silicon Marmosets, the value of Vr is typically in the range-from 1 to 3 V. Suppose that Vr = 2 V and that Vas is set to some value greater than Vr, say, 10 V. We will consider what happens when the drain-to-source voltage is gradually increased above 0 V. As Vos increases, the drain current increases because of normal Ohm’s law action. The current rises linearly with Vos, as shown in Figure 7-35. As Vm continues to increase, we find that the channel becomes narrower at the drain end, as illustrate ed in Figure 7-34. This narrowing occurs because the gate-to-drain voltage becomes smaller when Vos becomes larger, thus reducing the positive field
at the drain end. For example, if VGS = 10 V and Vos = 3 V, then VGD = 10 – 3 = 7 V. When Vos is increased to 4 V, VGO = 10 – 4 = 6 V. The positive gate-to-drain voltage decreases by the same “mount that Vns increases, so the electric field at the drain end. is reduced and the channel is narrowed. As a consequence, the resistance of the channel begins to increase, and the drain current begins to level off. This leveling off can be seen in the curve of Figure 7-35. When Vos reaches 8 V, then VaD = 10 – 8 = 2 V. = VT• That is, the positive voltage at the drain end reaches the threshold voltage and the channel width at that end shrinks 10 zero. Further increases in Vm do not change the shape of the channel and the drain current docs not increase any further If) saturates, This action is quite similar to the saturation that occurs at pinch-off in a junction FET. When the process we have just described is repeated with ViiS fixed at 12 y, we find that saturation occurs at Vns = 12 – 2 = \0 V. Letting V/ present the voltage at which saturation occurs, we have. in the general case,

Posted on November 18, 2015 in FIELD-EFFECT TRANSISTORS

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