Because the voltage-divider bias circuit (Figure 6-11) has been so widely used. certain practical, time-tested guidelines have evolved for its design. It has been found that reasonable compromises between stability, gain, and output swing can be achieved by designing the bias circuit in accordance with two basic criteria. First

the emitter-to-ground voltage should be approximately one-tenth of the Vcc sure voltage. Second, the current R2 should be approximately 10 time h the dc base current IN’ The latter criterion is met if the input resistance looking into the base is 10 times greater than R2 As discussed earlier. this restaurant ·c ratio

must be large to make the base voltage insensitive to f3 variations. and to a us

to neglect the loading effect of the base on the voltage divider. The two criteria are met if the following approximations are satisfied by the design: Vf 0.1 Vl R2.,.. {:I(min)R, (6-2(1) «(1-27. where l3(min) is the minimum value of {3 that transistors used in the circuit may have. In the absence of other constraints imposed by a particular application. the conditions expressed by equations 6-26 and 6-27 will lead to a design that has good de and ac performance characteristics. Our development of a design procedure based on these conditions begins with the assumption that the quiescent values of Vn: and (V(! and 1(J in Figure 6-11) are specified. i.e .• known constants. The objective is to find values for Rc, RE• RI, and R2 that set the required Q-point and simultaneously satisfy the two design criteria. In most practical design problems. the value of the supply voltage, V is predetermined by other system considerations,

and we will therefore treat it as a known constant. The first step is to find VE using the first of the two conditions: V 0.1 Vcc., Then, since RF.. = (6-Condition I )7 requires that Discrete Circuit Bias Design R! – ) Solving (6-32) for RI in terms of R~ leads to ( RI = R, Vce – I) – Vt:+ V/I/, (6-33) «Design a voltage-divider bias circuit in which Vce = 24 Y, V(I = 12 Y. and 1(1 = J mA. The circuit should perform satisfactorily using silicon transistors whose values of {3 range from 50 to 200. Solution”. From equation 6-26, V,: = 0.1(24) = 2.4 Y. From (6-2X), R, = (2.4 Y)/(I mA) = 2.4 kH. From (6-29) . .r Rc = (24 – 12 – 2.4) Y = 9.6 kO ImA From (6-33), From (6-34), RI = (12 x 1(}1)(2.4~ 0.7 – 1) = 80.9 kO The completed design. using the closest standard 5% resistors. is shown in Figure 6-1.2. Once a bias circuit has been designed. it should be analyzed to verify that the design specifications are satisfied, particularly if the resistors used have standard (precision) values that differ from the design calculations. 10 the case of this example. we find ( 12 X 1(}1 ) V 12 X J(}1+ 82 X 1(}I 24 V = 3.()6 Y v, = (3.06 – 0.7) Y = 2.36 Y

h I(! = 2.4 kll = 0.983 mA Vo ~ 24 V – (0.983 mA)[(9.1 kll) + (2.4 kll)] = 12.69 V We see that the actual quiescent values agree well with those required of the design.