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shown in Figure 7-3(a). This is as we would expect, since increasing the voltage across the fixed-resistance channel simply causes an Ohm’s law increase in the current through it. As we continue to increase VI)S, we find that noticeable depletion regions begin to form in the channel, as illustrated in Figure 7-3(b). Note that the
depletion regions are broader near the drain end of the channel (in the vicinity of point A) than they are near the source end (point B). This is explained by the fact that current flowing through the channel creates a voltage drop along the length of the channel. Near the top of the channel, the channel voltage is very nearly equal to Nos, so there is a large reverse-biasing voltage between the N channel and
the P gate. As we proceed down the channel, less voltage is available because of the drop that accumulates through the restive N material. Consequently, the reverse-biasing potential between channel and gate becomes smaller and the depletion regions become narrower as we approach the source. When Nos is increased legal~m. expand Ana toe Cezanne becomes very narrow in the vicinity of point A, causing the total resistance of the channel to increase. As a consequence, the rise in current is no longer directly proportional to Vos. Instead, the current begins to level off, as shown by the curved portion of the plot in Figure 7-3(a). Figure 7-4(a) shows what happens when VDS is increased to a value large enough to cause the depletion regions to meet at a point in the channel near the drain end. This condition is called pinch-off At the point where pinch-off occurs, the gate-to-channel junction is reverse biased by the value of Vos, so (the negative of) this value is called the pinch-off voltage, VI’. The pinch-off voltage is an important JFET parameter, whose value depends on the doping and geometry of the device. VI’ is always a negative quantity for an N-channel JFET and a positive quantity for a P-channel JFET. Figure 7-4(b) shows that the current reaches a maximum value at pinch-off and that it remains at that value as Vos is increased beyond I VI’I. This current is called the saturation current and is designated loss-the D rain-to-Source current with the gate Shorted.  Despite the implication of the name pinch-off. note again that current continues to flow though the device when Vos exceeds IVI.I. The value of Ih~ current remains constant at loss because of a kind of self-regulating or equilibrium process that controls the current when Vos exceeds  Suppose that an increase in Vos did cause Io to increase; then there would be in the channel an increased voltage drop original value. Conversely, if current ceased to flow at pinch-off, the depletion region would shrink and current flow  resume. Of course, tbs .change in current never actually occurs; 10 simply remains constant at loss- A typical set of values for Vp and loss are -4 V and 12 rnA, respectively. Suppose we connect a JFET having those parameter values in the circuit shown in Figure 7-5(a). Note that the gate is no longer shorted to the source, but a voltage Vas = -1 V is connected to reverse bias the gate-to-source junctions. The reverse bias causes the depletion regions to penetrate the channel farther··along the entire length of the channel than they did when V(;s was O. If we now begin to increase VDS above 0, we find that the current 10 once more begins to increase linearly, as shown in Figure 7-5(b). Note that the slope of this line is not as steep as that of the VGS = °line, because the total resistance of the narrower channel is greater than before. As we continue to increase Nos, we find that the depletion regions  again approach each other in the vicinity of the drain. This further narrowing of its resistance and undercurrent again begins to level off, Since  here is already ~m:1~V reverse bias between the gate and the channel, the intercommunication. ,w.hde the. depletion regions meet, is now reached at VIlS = 3 V listeria of 4 V'(VIlS-= Vus – V/.). As shown in Figure 7-5(b), the current saturates .at the lower value of 6.75 mA as VDS is increased beyond 3 V. If the procedure we have just described is repeated with VGS set to – 2 V instead of -{ V, we find that pinch-off is reached at Vos = 2 V and that the current saturates at In = 3 mA. It is clear that increasing the reverse-biasing value of VGS (making VGS more negative) causes the pinch-off condition to-occur _at smaller values of Vvs and that smaller saturation currents result. Figure 7-6 shows -the family vi characteristic curves, the drain characteristics, obtained when the procedure is Uniformed for VGS = 0, -1, – 2, -3,. and -4 V.The dashed line, which is parabolic joins the points on each curve where pinch-off occurs. A value of VD.\ on the parabola is called a saturation voltage V OS( su”, At any value of Vc;s, the corresponding value of) is the difference between VliS and VI’: VUS(s.t) VGS – VI” as we have already c;described. The equation of the parabola

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Posted on November 18, 2015 in FIELD-EFFECT TRANSISTORS