The general form Dr the algebraic solution for the bias point in a voltage-divider bias circuit can be found by solving the square-law equation (7-2) simultaneously with the bias-line equation (7-11 or 7-)2)_ The results, shown in equations 7-13, are valid for both P-channel and N-channel devices, since absolute values are used in the computations. The computed values must be checked to verify that the solution is in the pinch-off region: Sliver > IV/II – DVR;.d. Note that equations 7-13 reduce to equations 7~P.for self-bias when 0 is substituted for Vc;.The P-channel JFET in Figure 7-21 has the transfer characteristic shown in Figure 7-22. Determine the quiescent value of Iv (1) graphically and (2) algebraically Field-Effect Transistors The bias line joining the points (0 mA, -4 Y) anti (2.42 mA, 0 Y) is shown drawn on the transfer characteristic in Figure 7-22. It can be seen that the bias line intersects the characteristic at the quiescent value 10 = 4 mA. . 2. From Figure 7-21, R 1(, = 1.65 k!l, and V/= 20 V. From lhe transfer characteristic in Figure 7–22. we see that V” = S Y and 10.ls = 18 mA. We have already found (in part I) that VG = -4 Y. With reference to equations 7-13,Also notc that we must specify the value of VTO at – 5 rather than +.5, despite the fact that the JFET is a P-channel device. Figure 7-23(b) shows the results of a program run. We see that I(VIDS). the drain current. is 4.D22 mA; V(3, 2), the value of Vo.~.is -5.lJ23 V; and V(I. 2), the value of Vt;s, is 2.636 V. These values are in close agreement with those found in Example 7-X.
JFET BIAS DESIGN
The design of a JFET bias circuit requires that we find values for Ro. Rs. and/or R, and R, that produce specified values of In and Vvsgiven a supply voltage Yo/). Equations 7 J 5 for the self-bias circuit are found by solving equation 7-7 for Ro and by solving equation 7-5 or 7-6 simultaneously with the square-law equation
for Rs. The results can be used for either N-channel or P-channel designs. since absolute values of V” and V Oil arc used in the computations.voltage divider bias circuit for N- and P-channel JFETs. Note that a value for Ve can be assumed or can. be determined if the. range through which the bias point can be allowed to change is specified. Figure 7-24 illustrates the computation. The characteristic curves represent the range over which the JFET characteristic may change. A line drawn through the bias points that are desired when the characteristic changes, (Vc;.n, 1m) and (V 02)’ will intersect the horizontal axis at the required
value of VG. This value can be computed from the slope of the ‘bias line, as shown in Figure 7-24. , Given a value for Vr.. the voltage-divider resistor R, can be found as shown in equations 7-16, by assuming a value for R~. R2 will usually be smaller than R,. so
R~ sets an upper limit on the input resistance of the circuit.An N-channel JFET is to be biased at VDS = 6 V using a 15-V supply. The nominal Characteristic has Vp :-3.5 V and loss Batsman. The quiescent drain current should not xary more than ±O.5 mA from a nominal value of 6 mA when the JFET characteristic changes from Vp =, – 3 V to.V, =-4 V, with a corresponding change in loss from 12 mA to 15 mA, Find values for Rv, Rs, RJ, and R~ in a voltage- , divider bias design. Find the actual range of rD over the range o(the JFET characteristic~hep !he standard-valued 5%..resistors~st,to the calculated values are used in , the design .. Assume, the restorers have their nominal values.Solution. We must first find a value for Ve using the procedure illustrated in Figure 7-24. Thus, we must find the values of VGS2 and VGS1 corresponding to lin = 6.5 mA and ID’ == 5.5 mA when the JFET characteristic changes through the specified The standard-valued 5% resistors closest to the calculated values are Rs .., 390 n, RIJ = 1.1 k~, R, = 3.6 MO, and R2 = 330 kG. Using these values in equations 7-1 S, we find that I D ranges from 5.65 mA to 6.65 mA and VDS ranges from 5.09 Y to 6.58 Y, over the range of the JFET characteristic