Equations 7-4 are the equations of the load lines for N- and P-channel JFETs and each can be plaited on a set of drain characteristics to determine a Q-point. This technique is the same as the one we used to determine the Q-point in a BJT bias circuit. The load line intersects the Vos-axis at Voo and the In-axis at/ Ro· Example 7-.1 The JFET in the circuit of Figure 7-13 has the drain characteristics shown in Figure 7-14. Find the quiescent values of 10 and when (I) Leis = -1.5 V, and (2) = -0.5 V 1. The load line intersects the Vos-axis at VO/J= +16 V and the IJI”axis at 10 = (16 V)/(2 kO) = 8 mA. It is plotted on Figure 7-14. At the intersection of the load line with Veis = -1.5 V (labeled 0,). we Ind the quiescent values 4 mA and V H V. 2. The load line is. of course. the same as in part (I). Changing Vc;s to -0.5 V moves the Q-point to the point labclcdQ, in Figure 7-14. Here we See that 6.8 mA and Vn 2.4 V Part 2 of preceding example illustrates an important result. Note that changing S to -0.5 V in the bias circuit of- Fig-me 7 -13 caused the Q-point to’VC out of the pinch-off region and into the voltage<,>controller-resistance region. As we have already mentioned, checkpoint must be idiocy in tire pinch-off regionfur normal amplifier operation. To,/-“{is/-oJ>’, lite ‘(icscen I »of(.1’/ be greater lit all IVeiS I. The pi-off vol tag!’ for the .ievicc whose characteristics arc in 7″714 can be seen to l)c . “”proximately -4 V. Since I\leosl = 0.5 \1 and the q~ljescelll value of \at 0: is oi11y 2.-l V. we do not satisfy.the requirement: is therefore in till’ variahlc-rcxistnncc rcuiou. ” or course, the quiescent value fit’ I C III ulsu be determined using the trunsf’er characteristic of a JFET. Silll” characteristic is a plot or Ii, versus \lei’, it is only necessary to locat c lhrdiruuc and read the corresponding value or I” directly. The value u: ViI.\ can then be determined using equation 7 While graphical technique- (’01 \.llatil1t,!. the bias arc instructive ;1I1d provide insights to the way in which the circuit variables affect each other, the quiescent values of 10 and Vas can. be calculated using a straightforward computation, if the values of Vpand loss are known. The next example illustrates that the square-law characteristic. is used in this computation.Given that the JFET in Figure 7-13 has loss = lOmA and VI’ = -4 V, compute’ the quiescent values of 10 and V/lS when VGS = ,-1.5 V. Assume that it is biased in ine pinch-otf region”From equation 7-3, Vas VDD – ID RD = 16 – (3.9 mA)(2 kO) =: 8.2 V. These’ results are in close agreement with those obtained graphically in Example 7-3. Note that it was necessary to assume that the JFET is biased in the pinch-off region, to justify the use of equation 7-2. If the computation had produced a value of VDS less than typl Was! = ?.5 V, we would have had to conclude that the device is . not biased in pinch-off and would then have .had to use another means to find the Point. The values of loss and Vp are likely to vary widely among. JFETs of a given type. A variation of 50% is not unusual. When the fixed-bias circuit is used to set a Q-point, a’ change in the parameter values of the’ JFET for which the circuit was designed (caused, for example. by substitution of another JFET) can result in an intolerable shift -in quiescent values. Suppose, for example, that a JFET having parameters I f)SS = 13 mA and VI’ = -4.3 V is substituted ‘into the bias circuit of Example 7~3 (Figure 7-13), with VGS once again set to -1.5 V. Then . These results show that 1D increases 41.3% over the value obtained in Example 7-3 and that VI;s decreases 68,7%. Note also that the value of Vos (4.98 V) is now perilously near the pinch-off voltage (4.3 V). We conclude that the fixed-bias circuit does not provide good Q-point stability against changes in JFET parameters. Figure 7-15 shows a bias circuit that provides improved stability and requires only a single supply voltage. This bias method is called self-bias, because the voltage drop across R, due to the flow of quiescent current determines the quiescent value of VG, We can understand this fact by realizing that the current 10 in resistor Rs . creates the voltage source terminal, with respect to ground. For the N-channel JFET, this that the source is positive with respect to the gate, since the gate is grounded. In other words, the gate is negative (by volts) with respect to the source, as required for biasing an N-channel JFET: VGS = -. For tile P-channel device, the gate I~ positive by volts, with respect to the source