Phase Lockedloops Electronics Help

A phase-locked loop (PLL) is a set of components that, through the use of feedback, generate a signal whose frequency tracks that of another externally connected input signal. The term phase-locked is derived from the fact that the (apparent) phase difference between two signals of different frequencies is used to control, or maintain, the frequency of the output, as wiII be discussed in more detail.presently. Entire books have been written on the many applications of PLLs, particularly in signal processing and communications equipment, but we will discuss just two of the most common: FM demodulation and frequency synthesis.

A block diagram of a phase-locked loop. Note the voltage controlled
oscillator (yea), which (as will be discussed in Section 15-7) produces a signal whose frequency is proportional to input voltage. The output of the yea is connected to a phase comparator, which generates an output voltage proportional to the difference in phase between the yea signal and the externally connected input signal, V When the frequency of the input signal fluctuates, the output of the phase comparator is a tluctuating voltage that is, in effect, an error voltage proportional to the difference uifrequency between the two inputs to the comparator. The fluctuating error voltage is smoothed by the low-pass filter and applied to the input of the yea. The system is designed so that the error voltage causes the yea to adjust its frequency to match the frequency of ViII’ When the yea frequency and the frequency of ViII arc equal, the loop is “locked” at that frequency. Strictly speaking, phase difference is not defined for two signals having different frequencies. However, the phase comparator “sees” an apparent phase difference when the frequency of one of its inputs changes, as illustrated . We see that a small frequency difference creates a small (apparent)” phase difference and a larger frequency difference creates a larger apparent phase difference. By considering how these diagrams would appear if one frequency were very much larger than the other, we can understand why a practical PLL may not achieve lock
in such a situation without some design modifications.

Posted on November 18, 2015 in SPECIAL PURPOSE CIRCUITS

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