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Figure 7-36 shows a set of drain characteristics resulting from repetitions of the process we have described. with set 10 different values of positive voltage. When ViiS is reduced 10 the threshold voltage Vr = 2 V, notice that If) is reduced to 0 for al\ values of Vos. The drain characteristics are similar to those of an Nchannel JFET, except that all values of ViiS are positive in the case of the enhancement MOSFET. The enhancement MOSFET can be operated only in an enhancemcru rnodc, unlike the depletion MOSFET. which can be operated in both depletion and enhancement modes. The dashed. parabolic line shown 011 the characteristics in Figure 7-36 joins the saturation voltages, i.e., those satisfying equation 7-18. As in JFET characteristics, the region to the left of the parabola is called the voltagecontrolled- resistance regions where the drain-to-source resistance changes with VCiS, We will refer to the region to the right of the parabola as the active region. The  device is normally operated in the active region for small-signal amplification. Figure 7-37(a) shows the structure of a P-channel enhancement MOSFET and  its electrical connections. Note that the substrate is Nuype material and that a Ptype channel is induced by a negative VCiS. The field produced by VGS drives electrons away from the region near the insulating layer and inverts it to P rtateriul. Figure 7-37(b) shows a typical set of drain characteristics for the P-channel enhancement SAMOSET. Note that all values of VCI.~ arc negative and that the threshold voltage V,. is negative. N-channel :lnd P-channel MOSFETs ure often called NMOS and PMOS devices for short. Figure 7-3H shows the schematic symbols used to represent N-channel anJ Pchannel
enhancement MOSFETs. As in previous symbols. the arrow is drawn pointing into the device for an N-channel F[T and outward for a P-channel FET. The broken line symbolizes the fact that the channel is induced rather than being an inherent part of the structure.

Enhancement MOSFET Transfer Characteristic

In the active region. the drain current and gate-to-source voltage are related by where {J is a constant whose value depends on the geometry of the device. among other factors. A typical value of {J is 0.5 X 10-3 A1V2. Figure 7-39 shows a plot of the transfer characteristic of an N-channel enhancement MQSFET for which {J = 0.5 Xl0 .1 AIV~ and Vr = 2 V.

Enhancement MOSFET Bias Circuits

Although enhancement MOSFETs are most widely used in digital integrated circuits (and require no bias circuitry in those applications). they can. and occasionally do. find applications in small-signal amplifiers. Figure 7-40 shows one way to bias an enhancement NOS for such an application. This circuit appears to be identical to the bias circuit we used for an N-channel JFET (Figure 7-20 but it is quite different in principle. The resistor Rs does not provide self-bias as it does in the JFET circuit. Self-bias is not possible with enhancement devices; it can occur only in depletion devices. In Figure 7-40, the resistor R, is used to provide feedback for bias stabilization, in the same way that the emitter resistor does in a BJT bias circuit. The larger the value of Rs, the less sensitive the bias point is to changes in MOSFET parameters caused by temperature changes or by device replacement.  Recall that R, in a JFET self-bias circuit also provides this beneficial effect: We saw (Figure 7-18) that the greater the value of Rs, the less steep the bias line. Figure 7-4l shows the voltage drops in the enhancement MOSFET bias circuit. R, and R2 form a voltage divider that determines the gate-to-ground voltage The voltage divider is not loaded by the very large input resistance of the MOSFET so the values of R, and R2 arc usually made very large to keep the ac input resistance of the stage large. Writing Kirchhoff’s voltage law around the gate-to-source loop, we find (Note that III is considered positive in both consensual Writing Kirchhoff’s voltage
law around the drain-to-source loop, we find  Equation 7-25 is seen to be the equation of a straight line on ID-VGs-ax{‘s. It intercepts the In-axis at !R, and the Vc;s-llxis at Vc;. The line can be plotted on
the same set of axes as the transfer characteristics of the device, and the point of intersection locate’ the bias values of 10 and VGS

Posted on November 18, 2015 in FIELD-EFFECT TRANSISTORS

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