# The CMOS Analog Switch Electronics Help

The CMOS Analog Switch A CMOS analog switch, also called a bilateraL transmission gale, is formed by connecting an NMOS device in parallel with a PMOS device we shall presently  combination acts like two parallel newswires, both of which (‘r,p simultaneous Closed or simultaneously open. Actually, when t e switches are closed, both conduct small positive and negative signals, but only one conducts large positive signals, and the other conducts large negative signals.  Figure 8-48 shows how the devices are connected and the schematic symbol for the CMOS analog switch. Note that the PMOS substrate terminal is connected
to the most positive voltage and the NMOS substrate to the most negative voltage, labeled Vs. Notice that there are two inputs, labeled C and C. C (read: “C bar”) is the standard representation for the complement or inverse, of C. ‘I nus, if C is high, then C is low, and vice versa. These two inputs are the control inputs for the switch and determine whether the analog signal is passed from input to output or is shut off. Think of C and C as being obtained from the input and output of an inverter, not shown, and understand that we need only change t. e level of C to control the switch; the level of C will automatically b~the opposite of that of C. In the schematic symbol, the circular “bubble” at the C input is used to show that the input there is inverted. (For the sake of convention, we will few.ow this unfortunate and misleading notation; however, to be accurate, C instead of C should be shown connected to the bubble, since the bubble itself is usually regarded as performing the inversion operation.) It is helpful to analyze the operation of the CMOS analog switch in terms of specific parameter values, so let us suppose that VT is +2 V for the NMOS FET, -2 V for the PMOS FET, Voo == +5 V, and Vss == -5 V. Assume that the analog input can vary continuously between +5 V and -5 V, and that C and C arc either +5 V or -5 V. When C == -5 V, the gate of the NMOS FET is at -5 V and it is  therefore OFF for all input voltages in the range -5 V to.:::!-5V. (To be ON, the input would have to be more negative than -7 V.) Since C = +5 V, the gate of the PMOS FET is at +5 V and it is also OFF for all input voltages in the range -5 V to +5 V. (To be ON, the input would have to be more positive than +7 V.) We conclude that C = -5 V causes the analog switch to be open. Now suppose that C == +5 V. Then the gate of the Nethermost is at +5 V and it is ON for input voltages in the range -5 V to +3 V. Since C == -5 V, the PMOS FET is ON for nil input voltages in the range -3 V to +5 V. Between the two devices, there is a conducting path from input to output for the entire range of input voltages from -5 V to +5 V, and we conclude that C == +5 V closes the analog switch. Figure
8-49 illustrates the overlapping of the ranges of .input voltages for which each device conducts. It can be seen that both are conducting in the range of, input between -3 V and +3 V.8. What is the .alum of the trans conductance of a JFET when its gate-to-source voltage equals its pinch-off voltage? b. At what value of IIJ does g., = O? 8-2. Find the trans conductance of the JFET whose transfer characteristic is shown in Figure X-2, whcn I” = 1mA, both (a) graphically and (b) algebraically.Find the trans conductance of the JFET whose transfer characteristic is shown in Figure 8-2, when V(;s = -0.5 V, both (a) graphically and (b) algebraically Use equation 8-2 intl the equation, of the transfer characteristic of a JFET to derive equation 8-3. The maximum trans conductance of a certain
N-channel JFET is 9.8 x 10-3 S. If mA, what is its pinch-off voltage?

Posted on November 19, 2015 in FET CIRCUITS AND APPLICATIONS