# The Common-Source JFET Configuration Electronics Help

Figure 8-4 shows a common-source JFET amplifier with fixed bias Van. Ra is a large resistance connected in series with VaG to prevent the source from shorting the ac signal to ground. (Recall that a source is an ac short circuit.) The input re stance of the JFET is so large hat there is negligible de pottage vision at the gate; that is, the major part of VaG appear from gate-to-source instead of across Ra, so Vas = Vaa. From another viewpoint, the gate current is so small that there is negligible drop across Ra. The input coupling capacitor serves the same purpose it does in a BJT amplifier, namely, to provide isolation between the signal source and the FET. For the moment, we ignore any signal-source resistance (rs) and assume that the output is open (Rt = 00). The total gate-to-source voltage is the sum of the small-signal source voltage, Vs, and the bias voltage VaG. For example, if VGG = -2 V and Us is a sine wave having peak value 0.1 V, then vp == -2 + 0.1 sin cat volts. Thus, vp varies between the extreme values -2 – 0.1 = -2.1V and -2 + 0.1 = -1.9 V. When vp goes more (toward – 1.9 V), the drain current increases. This increase in id causes the output voltage v,’s to decrease, since

We conclude that an increase in the input signal voltage causes a decrease in the output voltage and that the output is therefore 1800 out of phase with the input. Figure 8-5 slows the equivalent circuit of the common-source amplifier in  Figure &~4, \’~th the JFET replaced by its small-signal equivalent. The coupling capacitor is assumed to have negligible impedance at the signal frequency we are considering (for now). so it is replaced by ;\ short circuit. As sources are treated as ac short circuits to ground. Notice that the arrow in the controlled current source can be shown reversed (from Figure 8-3) with a minus sign attached.  Note: If arrow is reversed, minus sign must be attached (not “can be”). The minus sign ,denotes the phase inversion between input and output. as we have described. It is clear from Fig u .p-5 tha The JFET in the amplifier circuit shown in Figure 8-6 has IIJSS = 12 mA, VI’ =
-4 V, and rJ = 100 kO.
1. Find the quiescent values of II) and Vos.
2. Find gm’
3. Draw the ac equivalent circuit.
4. Find the voltage gain .

Bias-Stabilized JFET Amplifiers

The JFET amplifier we have been studying employs the fixed-bias method for setting the Q-point. Recall from Chapter 7 that this method makes the Q-point sensitive to parameter changes and is therefore undesirable in any application where JFET parameters may vary. Figure 8-8 shows a common-source JFET amplifier using the improved bias method that incorporates self-bias and a voltage divider across the gate. Note the source bypass capacitor connected in parallel with Rs. This capacitor serves the same purpose as the emitter bypass capacitor in a BJT common-emitter amplifier, namely, to eliminate the ac degeneration that would  otherwise occur due to part of the output signal being dropped across the resistor. As far as the ac signal (Vds) is concerned, the source is grounded, and there is no loss across Rs. Of course. the de voltage VDS is unaffected by the capacitor, so Rs continues to ‘serve its role in providing ‘self~via & for the JFET. Figure 8-9 shows the ac equivalent circuit of the bias-stabilized amplifier in Figure 8-8. Notice that R, and R2 appear in parallel to ac signals, so fill = R, It R2: These resistors are made quite large to maintain a large input resistance to the amplifier. The voltage gain of the bias-stabilized amplifier is derived in exactly the same way and has exactly the same value as the Fixed-bias amplifier, assuming no signal source resistance: Au = -gm(rd II RD) = -gm RD’ When the JFET amplifier is biased using only the self-biasing resistor (no voltage divider), the voltage gain is again computed using Au . A resistor Ra is connected between gate and ground to provide continuity for the gate circuit. This resistor can be made very large to maintain a large input resistance to the amplifier. The reverse current through the reverse-biased gate-source junction is very small, so the voltage drop across Rc; is negligible. However, if an extremely large resistance is used with a JFET having excessive leakage current,
the drop should be taken into account. For example, if Rc = 10 MO and = 0.1 JLA, 11 gate voltage will be increased by = 1 V Figure 8-11 shows the common-source amplifier he Real bias Range with load and signal-source resistances included. Also shown are the ac equivalent circuits of each. Note in each case that rs is in series with the amplifier input and RJ. is in parallel with the amplifier output. For the fixed-bias amplifier (Figure 8-11(a», equation 8-11 becomes.

Posted on November 18, 2015 in FET CIRCUITS AND APPLICATIONS