# THE JFET AS AN ANALOG SWITCH Electronics Help

An analog switch is an electronically controlled device that will either pass or shut elf a cotter~ “varying .Figure 8-24 iIlustr res the concept. By way of contrast, digital switch is one whose output switches between oal possible levels (low or high), such as the BJT inverted we discussed in 4. As illustrated in Figure 8-·24,the analog switch is “opened” or “closed” by Q ~invigilate input. Depending on the nature of the device, a h may close the switch and a low input may open it; or vice versa. An analog switch is al~ called a aigital analog switch (DAS) because a digital input controls the switching of an analog .signal.  A JFET can be used as an analog switch by connecting it as shown in Figure 8-25. j iotc thai the analog signal v is connected to R», where a fixed supply voltage (VDI) would normally be connected. The digital signal that opens and closes the switch is the gate-to-source voltage VGS. VGS is either 0 V, which causes the JFET to conduct, or Vp, a negative voltage (for an N-channcl JFET) that cuts the JFET off. The output voltage of {he switch, v••, is the drain-to-source voltage, which will be either VJ (when the JFET is cut off) or close 0 (when the JFET is conducting). Note that the switching arrangement is somewhat different from that shown in Figure .8-24, because the switch is now in parallel with the load resistance R,.. When the switch is closed (JFET on), it effectively shorts out RL; when the switch is open (JFET cut off), the short is removed. When used as an analog switch. the JFET is operated in its voltage-controlled resistance region rather than in pinch-off. As an aid in understanding how the JFET operates as a switch. refer to Figure 8-26, which shows a portion of the drain characteristics for Vos = 0 and for Vas = Vp- Only the rising portion of the V GS = oC\l~<;. in the voltage-controlled-resistance region is shown. The line corresponding to Vas = Vp coincides with the horizontal axis, since 10 = 0 in this case. Imagine that the variation in tJd creates a series of parallel load lines, each intersecting the Vos-axis at an instantaneous value of Vd, just as a load line would intersect at V00 if a fixed drain supply voltage were present. Thus, when Vos = Vp, the values of Vvs arc the same as the variations in Vd’ This condition corresponds to that shown in Figure 8-25(c). When Vos = 0, the operating point moves to the Vas;: 0 curve and the output voltage (lIDS) is very small. This corresponds to Figure 8-2S(b). As long as Vc;s remains at O. the variations in In and Vns are traced by a point that moves up and down the VGS = 0 curve. For small variations, the curve is nearly linear and can be seen to be quite steep. The resistance (~VIM) in this region is therefore very small and approximates the short-circuit condition we discussed for the case when the PET is “00” (conducting). Note in Figure 8-26 that the Vc;s = 0 curve extends into the third quadrant: the region where V,’S is negative and la is negative. This is the region of operation when the analog signal V,I goes negative and the current through the channel reverses direction. The reversal of polarity causes the gate-to-source junction to be forward biased but does not affect the channeL resistance, so the slope of the VGS = 0 curve is unchanged. The total variation in Vd must be small so that operation takes place over a small, nearly linear portion of the Vas = 0 curve on either side of the origin. Also, Ro must be large enough to ensure that the variation occurs along the lower portion of the Vas = 0 curve; that is, the load line should not be steep. When the JFET is conducting, the small resistance VDslID = vds1id in the region around the origin is called the ON resistance, RO(ON). Typical values range from 20 to 100 ohms. The smaller the value of RO(ON» the more nearly ideal the switch. While a BJT switch has a lower ON resistance, the JFET switch has the advantage that id = 0 when Vd = O.

Posted on November 18, 2015 in FET CIRCUITS AND APPLICATIONS