BJT constant-current sources were discussed extensively in Chapter 6 (Section 6-H). A JFET can be used to supply constant current to a variable load by connecting its gate directly to its source, as illustrated in Figure 8-21. Here, the resistor UII is regarded as the (variable) load resistance. To be able to supply a current th.u is independent of RIl, the JFET must remain in its pinch-off region. Re~11Ithat the condition for pinch-off is IVDSI > IV, I – lVasl. Since Vas = 0 in this case, the condition reduces to The constant current produced by the JFET is then II) = lnss, because that is the drain current in the pinch-off region when Vas = O. So long as the JFET is in its pinch-off region, the line corresponding to V,.s = o is essentially horizontal, meaning that the same current flows regardless of V,’S’ See Figure 8-22. In reality, the line rises slightly to the right, so the current source  is not perfect. Of course, no current source is perfect. The JFET current source would be perfect if ‘J were infinite, which would be the case if the line were
herizontal: ‘” = 6. Vosl6.l/l with 6.10 = O. The JFET can also be used to supply a constant current equal to some value less than loss by biasing it appropriately.

Common·Gate Amplifier

Figure 8-20 shows a common-gate amplifier and its small-signal equivalent circuit. We see that the load voltage is developed across the parallel combination of rd. R/l. and R We see that the magnitude of this gain is calculated in the same way as it is for the common-source amplifier. Note, however, that the gain is a positive quantity.
so there is no puese ;nv’lfsion between input and output. When signal-source resistance rs is taken into account, voltage division occurs at the input, and the gain VI/VS becomes The input resistance of the common-gate amplifier is 1m:.:::. :’~j}-¥’krthan its commonsource and common-drain counterparts. Using the typical values gm =4000 ~S und Rs = 500 0, we find ,;,,{stage) = (114000 JLS) II(500 H) = (.~:;o0)11(500 0) = l&.i.7 O. To avoid the large reduction in voltage gain predicted by equation 8-33 when such a small value of ‘;n{stage) is used, it is clear that signal-source resistance rs must be very small.

Posted on November 18, 2015 in FET CIRCUITS AND APPLICATIONS

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