Thus, (-3 Y, 5 mA) is another point on the bias line. We can then draw a straight line between the two points (0,0) and (- J V, 5 mA) and note where that line intersects the transfer characteristic. The line is plotted on the-transfer characteristic shown in Figure 7-17. We note that it intersects the characteristic at If) “.. 3 mA, which is the quiescent drain current. The.corresponding value.of V(iS is seen to be approximately -1.8 V. The quiescent value of Vvs,is found from .equation 7-‘7:

**Gerieral Algebraic Solution-Self·Blas**

The quiescent values of in and VGS in the self-bias circuit can also be computed algebraically by solving the bias-line equation and the square-law equation simultaneously. To perform the computation, we must know the values of luss and Vp. As in the fixed-bias case. the results are valid only if the Qvpoint is in the pinch-off region, i.e., if iVnsl > iV”I – iVlisl. We must therefore assume that to be the case,

but discard the results if the computation reveals the quiescent value of IVfl.~lto he less than iV,.1 – We Equations 7-‘l{ give the general form or the algcbr.i:c ple 7-5. Solution. As shown in Figure 7-16. Rs = 600 il and RD = 1.5 kil. Also. the transfer characteristic in Figure 7-F shows that l nss = 10 mA and Vp = -4 V. Thu .•, with reference to .equations 7-8, we find Since the JFET is N-channel, Vas = -1.8 V. These results agree well with those found in Example 7-5. Since IVDSI = 8.7 V > IV”I – IVcsI = “4 V – 1.8 V = 2.2 V, we know the bias point is in the pinch-off region and the results are valid. To demonstrate that the self-bias method provides better stability than the fixed-bias method. let us compare the shift in the quiescent value of ID that occurs using each method, when the JFET parameters of the previous example are changed to tss«> 12 mA and VI’ =’ ..,.4.5 V. In each case, we will assume that the initial bias point (using a JFET with less = 10 mA and VI’ = -4 V) is set so that III = 3 mA and that a JFET having the new parameters is then substituted in the circuit. We have already seen that 10 = 3 mA when Vas = -1.8 V, so let us suppose that a fixed-bias circuit has Vas set to -1.8 V. When loss changes to 12 mA and VI’ to’ -4.5 V, with Vr;.I’ fixed at -1.8 V, we find that the new value of III in the fixed-bias circuit iThis-change in If) from 3 mA to 4.32 mA represents a 44% increase. Suppose now that the JFET parameters in the self-bias circuit change by the same amount: loss = 12 mA and Vp = -.4.5 V; Using equations 7-8, we find If) = 3.46 mA. In this case, the increase in ID is 15.3%, less than halfthat of the fixedbias design. Figure 7-l8 shows the transfer characteristic of the JFET having loss = 10 mA and VI’· = -4 V; ‘add the transfer characteristic corresponding to the JFET with loss = 12 mA and VI’ = -4.5 V. The self-bias line Vas = -6001f) is shown intersecting both characteristics. Note that it intersects these characteristics at the values of If) previously calculated for the self-bias circuit: 3 mA and -3.46 mA. Also shown is the vertical line corresponding to VGS = – 1.8 V-I.e., the line corresponding to the fixed-bias condition. This line intersects the characteristics at the two values previously calculated for the fixed-bias circuit: 3 mA and 4.32 mA. It is apparent in this figure why the self-bias method produces a smaller change in ID than the fixed-bias method when a change in JFET parameters results in a different transfer characteristic: The smaller the slope of the bias line, .the smaller the change in If) Voltage-Oivid.er Bias Our interpretation of Figure 7-18 reveals that good bias stability against changes in JFET parameters can be achieved by making the slope of the bias line as small as possible. The slope of this line ‘becomes smaller as R, is made larger, but large values of R« can result in unacceptably small values of If)’ One way to obtain a biasline having a small slope (large value of Rs) and still maintain a respectable amount of drain current is to connect a positive voltage V(m to the gate (of an N-channel JFET) in the self-bias circuit. This arrangement is shown in Figure 7-19(a). The effect of VGc; is to shift the intercept of the bias line on the horizontal axis to V(;(;. as shown in Figure 7-19(b). The equation of this bias line is In practice, the positive gate voltage is obtained from a voltage divideracross the gate from the positive supply voltage Villi’ For a the gate voltage is made negative and is obtained from the negative supply VIlIl. These connections arc shown in Figure 7-20. Since the input resistance at the. is very large, it is not necessary to consider its loading effect on the voltage divisive . Thus, the gate-to-ground voltage VI; for the N-channel JFET is determined from