Transfer Characteristics Electronics Help

Transfer Characteristics The transfer characteristic of a lFET is a plot of output current versus input voltage. for a fixed value of output voltage. When the input to a JFET is the gate-to-source voltage and the output current is drain current (common-source configuration).
the transfer characteristic can be derived from the drain characteristics. It is only necessary to construct a vertical line on the drain characteristics (line of constant VIlS) and to note the value of III at each intersection of the line with a line of constant Vc;s. The values of I/J can then be plotted against the values of Vc to construct the transfer characteristic. Figure 7-10 illustrates the process. In Figure 7-10. the transfer characteristic is shown for Vos == H V. As can be seen in the tigurc, this choice of VIJS means that all points are in the pinch-off region. For example. the point of intersection of the V”.I = H V line and the VI;s == o V line occurs at III == l ns» == 12 mA. At V/l.\’ == 8 V and VC;.I== -I V. we find III ::: 6.75 mA. Plotting these combinations of II> and VI;” produces the parabolic transfer characteristic shown. The nonlinear shape of the transfer characteristic can be anticipated by observing that equal increments in the values of Vc;s on the drain characteristics (6VI;s == I V) do not produce equally spaced lines. (Recall from our discussion of BJT output characteristics that this situation creates output signal distortion when the device is used as an ac amplifier; practical Jf’E’Tcircuits incorporate a means for reducing distortion, at the expense of gain. that we will discuss in a later chapter.) Note that the intercepts of the transfer characteristic arc Il>n on the In-axis and \I” on the Vc;s-axis. The equation for the transfer characteristic ill the pinch-off region is. to a close approximation, Note that equation 7-2 correctly predicts that Iv = loss when ViiS = 0 anJ that III = 0 when VC;.I’ = V”, The transfer characteristic is often called the square-law characteristic of a JFET and is used in some interesting applications to produce outputs that arc nonlinear functions of inputs,Note Ihat we step VGS from () to -2 V in 0.1- V increments. The voltage source labeled VUS has its positive terminal connected to the gate of the FET. hut the stepped voltages should all be negative. (Alternatively. we could reverse the polarity
of V(iS and step it through positive voltages.) The voltage source labeled VIDS is a dummy source used to obtain positive values of drain current. The .PLOT statement  produces a riot of I(VIDS) (i.e., loci) versus VGS, which constitutes a transfer characteristic. . Figure 7-11 (b) shows the plot produced by SPICE. (Rotate it 1800 to obtain the orientation shown in Figure 7-10.) Note that 10 = 10 mA = loss when Vri.1 = o and that I/) “‘” 0 when Vus = V”. Although the values of printed down the left margin should all be negative, SPICE prints only the absolute values of the independent variable associated with a .PLOT statement, which is Vein in this example.


Fixed Bias Like a bipolar transistor, a JFET used as an ac amplifier must be biased in order to create a output voltage around which ac variations can occur. When a J FET is connected in the C(}IIII//(}/I-S()tI/l’C’ configuration. the input voltage is \I(iS and the
output voltage is V”.I’ Therefore, the bias circuit must set de (quiescent) values for the drain-to-source voltage V”s and drain current I”. Figure 7-12 shows one method that can be used to bias N-channel and P-channel JFETs. Notice in Figure 7-·12 that a de supply voltage V/l1I is connected to supply drain current to the JFET through resistor R/), and that another de voltage is used to set the gate-to-source voltage V(iS’ This biasing method is called fixed bias because-to-source voltage is fixed by the constant voltage applied across those terminals. Writing Kirchhoff’s voltage law around the output loops in Figure 7-12, we find When using these equations, always substitute a positive value for \.ill[) to ensure that the correct sign is obtained for Vos. VDS should always turn out to be a positive quantity in an N-channel JFET and a negative quantity in a P-channel JFET. For example, in an N-channel device where Voo is +15 V from drain to ground, if 10 = 10 mA, and R[) = 1 kO, we have V/Js = 15 – (10 mA)(l kO) = +5 V. For a P-channel device where Voo is -15 V from drain to ground, VIlS = -15 + (10 mA) X (1 kO) = -5 V. Equations 7-3 can be rewritten in the form

Posted on November 18, 2015 in FIELD-EFFECT TRANSISTORS

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