VMOS Transistors ~till another variation in MOS structure is called VMOS, which is used to produce both N-channel and P-channel enhancement MOSFETs. The name is derived from the appearance of the cross-sectional view (Figure 7-48), in which it can be seen . -shaped groove penetrates alternate Nan P layers. (In reality, the device i Corridor in a crater shaped like an inverted pyramid.) As can be seen in the Channel VMOS transistor shown in Figure 7-48, the length 01′ the induced N channel is determined by the thickness of the P layer. The layers are formed using epithelial growth and diffusion methods, which provide good control over thickness and therefore good control of channel length. Since the aspect ratio of the channel determines some important properties of the FET, this control is a valuable feature of the method. Also, the technique conserve” space on the chip surface because the channel can be made longer simply by making the P region thicker. As a result, a greater number of devices can be created in one chip using conventional photo lithographic methods. Finally, VMOS transistors have greater current- handling capabilities than their planar counterparts and are finding use in power amplifier applications. DMOS Transistors DMO i an FET structure created specifically for high-power application . It is a planar transistor whose name is derived from the double-diffusion process used to construct i·. Figure 7-49(a) shows a cross-sectional view. Note that drain-to-source current flow through a P-type channel region (that is inverted by a positive gate to- source voltage), an N- (lightly doped) ‘epithelial region, and an N+ substrate. The channel length can be closely controlled in the diffusion process and is typically very short (a few micrometers). For this reason, it is called a short-channel MOS transistor. DMOS transistors are widely used for switching heavy currents and high voltages, as in class D amplifiers (Section 15-11) and switching regulators (Section 16-8). The DMOS transistor has a parasitic diode between its drain and source. A parasitic component of a semiconductor device is one that exists as a result of the structure of the device rather than by design. In other words, the parasitic diode in a DMOS transistor is inherent in its structure of P and N layers: Its existence is inevitable. In Figure 7-49(a), the N” source and the P channel (called the body) form an electrical bond rather than a PN junction. The parasitic diode is the PN junction between the body and drain. Since the body is electrically connected to the source, the parasitic diode is effectively connected across the drain and source terminals, with anode connected to source and cathode connected to drain. The schematic symbol for the DMOS transistor often includes the parasitic diode, as shown in Figure 7-49(b} Field-Effect Transistors One property shared by short-channel power FETs is that they ‘,ave a 11 transfer characteristic. That is, when e gate-to-source voltage is g than the threshold voltage, the drain current is a Irucar function of the gate-to-source voltage rusher than the nonlinear function illustrated in Figure 7-39. The linear transfer characteristic of short-channel devices is the result of a phenomenon called velocity  saturation, whereby the velocity of charge carriers reaches but docs not exceed a certain value drain-to-source current increases. The linear ransack characteristic is illustrated and discussed in more detail in Section S-5

Posted on November 18, 2015 in FIELD-EFFECT TRANSISTORS

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